Protocols for transmitting high-speed serial data between devices are constantly in the process of being revised with new and improved versions. Examples of such protocols include the DisplayPort standard, the High-Definition Multimedia Interface (HDMI) standard, the Serial ATA standard, the Peripheral Component Interconnect Express (PCI-E) standard, and the Universal Serial Bus (USB) standard. However, such protocols often use input/output (I/O) paths with physical layer interfaces that dedicate specific I/O pins as inputs or outputs. Such specificity in I/O pin functionality increases deployment costs. For example, data centers with dense server deployments require complex cable routing due to geometrical constraints arising from fixed I/O pin layouts. Moreover, the fixed nature of I/O pin functionality can result in misallocation of upload or download throughput resources, since a particular physical channel (e.g., an upload channel) for an I/O pin cannot be used for a different purpose (e.g., as a download channel) in response to changing data traffic patterns.
Despite the evolution of such data communication protocols having yielded significant improvements in features such as data rates, there has been less significant advancement in I/O path flexibility. Conventional approaches to improving I/O path flexibility are associated with increased challenges for circuit designs for high-speed serial communications. For example, a conventional circuit design for increasing I/O path flexibility is a matrix of passive switches (“passive matrix switch”). As depicted in FIG. 1A, an example passive matrix switch design having four ports (P1-P4) includes four passive switch components, S12, S14, S32, and S34. Each of these passive switches allows signals to propagate in either direction between the enumerated ports. Unfortunately, the passive components in the passive matrix switch and/or channel cause signal bandwidth limitations and insertion losses that result in signal degradation unacceptable for high-speed serial communications.
Referring to FIG. 1B, in some conventional approaches to increasing I/O path flexibility, active components A1-A4 controlled by a digital state machine (not shown) are combined with a passive matrix switch to compensate for the signal degradation caused by the passive components. Such a combination of active components and a passive matrix switch is referred to herein as an “active matrix switch.” Unfortunately, the active components are unidirectional, in contrast to the bidirectional passive components. As a consequence, a conventional active matrix switch has two unidirectional active components interfaced to a passive switch (e.g., A1 and A2 are each coupled to switch S12), one dedicated for upstream traffic, and the other dedicated to downstream traffic. It should be appreciated that in certain applications, dedicated circuitry is balanced equally between upstream traffic and downstream traffic, but the amount of actual data traffic (e.g., data payload) can be heavier in one direction relative to another direction. For example, the downstream traffic can be higher than upstream traffic.
While a conventional active matrix switch helps to address the signal degradation caused by the passive components and/or channel, the parallel upstream and downstream branches contain redundant (i.e., duplicative) circuitry. For instance, for the example passive matrix switch design having four ports (P1-P4), four sets of circuitry having identical components are necessary (e.g., two sets to handle the paths from P1→2,4 and P3→2,4, and two sets to handle the paths from P2→1,3, and P4→1,3). Such redundancy is inefficient in terms of power and semiconductor die area usage, thereby limiting the ability of the conventional active matrix switch to meet the practical needs of circuits requiring I/O path flexibility.
An example deployment of a half-duplex signal repeater will be instructive. The signal conditioning performed by a signal repeater is a critical task in serial communication systems. Repeaters are used in a wide range of applications, including redrivers and retimers. One objective of repeaters is to regenerate signals to boost the signal quality of high-speed interfaces. Repeaters are a key technology for addressing the signal integrity challenges that higher data rates introduce across every industry and serial data protocol.
In an example deployment of a half-duplex signal repeater, such as in a hub device with signal regeneration capabilities, in the upstream path, the initial active component can be a Continuous Time Linear Equalizer (CTLE) to correct for losses and distortions caused by high frequency transmission lines and/or compensate for the insertion loss caused by the channel. This can be followed by, for example, a decision feedback equalizer (DFE) that uses feedback of detected symbols to produce an estimate of the channel output. For example, the intersymbol interference (ISI) can be directly subtracted from the feedback of detected symbols via a feedback finite impulse response (FIR) filter. The DFE can be followed by, for example, a unidirectional clock and data recovery (CDR) circuit for extracting timing information from a serial data stream to allow the receiving circuit to decode the transmitted symbols, which is necessary to generate a high fidelity replica of the received signal, thereby recovering the clock and data from the serial data stream. The unidirectional CDR can be followed by, for example, a driver circuit matched to the characteristics of a subsequent circuit stage, such as a USB 3.0 compliant cable connected to a host device. Continuing the example, in the downstream path, the initial active component receiving signals from the host device is a second CTLE, followed by another DFE, unidirectional CDR, and driver for driving a signal on a USB 3.0 compliant cable connected to a destination slave device.
It should be appreciated that, despite the increased flexibility of such a half-duplex signal repeater, there are still duplicates of circuitry such as the unidirectional CDR circuits. Such redundancy results in power consumption and semiconductor die area penalties. It should further be appreciated that that the scale of the penalties increases based on the number of I/O paths. For example, in a hub device with n slave ports, there is redundant circuitry for each of these ports, and therefore the power and area penalty is multiplied by n.
Such penalties in power and area can be substantial, even when n equals one. For example, to support the high data rates, communication circuits must satisfy stringent performance specifications, such as low bit error rates (BERs), which require unidirectional CDRs with low jitter components. Thus, unidirectional CDRs that support high-speed serial communications standards are often large and power-hungry circuits, as they typically include a main CDR loop and a multiphase generator circuit having a phase locked loop (PLL) or a delay-locked loop (DLL). As an example, a unidirectional CDR that supports high-speed serial communication standards can be large and power hungry because of the on chip loop filter and high frequency voltage control oscillator. The multiphase generator outputs multiple, phase separated signals approximating the incoming data rate and feeds them to the main CDR loop. Multiple phase detectors are used to detect the sign of the phase error, which is used to control the phase of the recovered clock signal in order to center the main CDR loop on the input data eye. In certain architectures, a high speed clock from the voltage control oscillator will feed the phase detector and compare the incoming data to produce early/late signals. These early/late signals are used to control the voltage control oscillator frequency so as to synchronize with the incoming data.
The design of unidirectional CDRs for high-speed serial communications is complicated by conflicting tradeoffs between linearity, noise sensitivity, operating voltage range, area, and power. For example, the loop filter's capacitance usually consumes the largest area due to capacitance density and/or leakage concerns. It should be appreciated that the leakage can be higher due to, for example, an increase in the number of devices being connected to the unidirectional CDR. The loop filter capacitance, when implemented on chip, consumes a large area, such as, for example, 50% or more of the die area for a retimer circuit. In additional to being large, the unidirectional CDR is also power-hungry due to, at least in part, the at-speed phase detectors and at-speed voltage controlled oscillator.
Conventional repeater (e.g., retimer, reclocker) designs with unidirectional CDR circuitry are not designed to be interfaced to a passive matrix switch in a manner that provides a power and size efficient active matrix switch.
One commercially available repeater circuit implements separate upstream and downstream channels and is described as having applications in bidirectional signal conditioning. The bidirectionality refers to a dual channel circuit, one channel being dedicated to transmit, and the other channel being dedicated to receive, with each channel having its own unidirectional CDR. Another example of a repeater circuit with separate upstream and downstream channels is described as a single channel bidirectional CDR. The repeater circuit is designed for the small form factor package (SFP28) physical interface, which is a full-duplex interface with simultaneous transmit and receive, such as through separate copper or fiber cables, or through a single fiber cable using wavelength division multiplexing. The single-channel refers to a full-duplex transmit/receive pair, therefore the bidirectional CDR of the repeater circuit refers to a dual channel circuit, one channel being dedicated to transmit, and the other channel being dedicated to receive, with each channel having its own unidirectional CDR. The circuit designs for the above two examples have two unidirectional CDRs, two output ports, two input ports, and no I/O ports, therefore the circuit designs are not intended to be interfaced to a passive matrix switch to provide a power and size efficient active matrix switch.
A different commercially available repeater circuit reduces the redundancy in active components, such as unidirectional CDRs, in upstream and downstream channels, and is described in the datasheet as a bidirectional I/O with integrated reclocker. However, the bidirectional I/O is limited to a single I/O port, the SDI_IO± port (for the purposes of the present disclosure, both a single ended I/O and a differential I/O interface are referred to as a single I/O). There is no second I/O port because the 100 ohm driver and PCB EQ active components have dedicated transmit and receive ports, respectively. In fact, the 100 ohm loopback output mode described in the feature list of the datasheet allows the 100 ohm driver and PCB EQ to propagate signals simultaneously, therefore the two active components would not be coupled to a shared physical channel to form an I/O port, as is illustrated for Cable EQ and Cable Driver active components coupled to the 75 ohm termination network. The 100 ohm driver and PCB EQ would not be configured to share a physical channel as that would increase the loading on a subsequent circuit stage, such as on the PCB, due to the PCB traces leading to the 100 ohm driver and PCB EQ active components. The circuit has one unidirectional CDR, two output ports, one input port, and one I/O port, and therefore the circuit is not designed to be interfaced to a passive matrix switch to provide a power and size efficient active matrix switch.